| Submitter | David Daney |
|---|---|
| Date | 2010-04-06 08:04:50 |
| Message ID | <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> |
| Download | mbox | patch |
| Permalink | /patch/1093/ |
| State | Accepted |
| Delegated to: | Ralf Baechle |
| Headers | show |
Comments
On Tue, Apr 06, 2010 at 01:29:50PM -0700, David Daney wrote: > The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they > are the same thing, for a 64-bit kernel they are not. > > It happens to kind of work on a 64-bit kernel as they both reference > the same physical memory. However since the CPU uses the CKSEG0 base, > determining if a J instruction will reach always gives the wrong > result unless we use the same number the CPU uses. Applied, thanks! Ralf
Patch
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7ce84bb..b122f76 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1706,7 +1706,7 @@ void __init trap_init(void) ebase = (unsigned long) __alloc_bootmem(size, 1 << fls(size), 0); } else { - ebase = CAC_BASE; + ebase = CKSEG0; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); }
The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they are the same thing, for a 64-bit kernel they are not. It happens to kind of work on a 64-bit kernel as they both reference the same physical memory. However since the CPU uses the CKSEG0 base, determining if a J instruction will reach always gives the wrong result unless we use the same number the CPU uses. Signed-off-by: David Daney <ddaney@caviumnetworks.com> --- arch/mips/kernel/traps.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)